JPS5442949A - Ternary converter circuit - Google Patents

Ternary converter circuit

Info

Publication number
JPS5442949A
JPS5442949A JP10913977A JP10913977A JPS5442949A JP S5442949 A JPS5442949 A JP S5442949A JP 10913977 A JP10913977 A JP 10913977A JP 10913977 A JP10913977 A JP 10913977A JP S5442949 A JPS5442949 A JP S5442949A
Authority
JP
Japan
Prior art keywords
output
converter circuit
fet
ternary converter
ternary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10913977A
Other languages
English (en)
Japanese (ja)
Other versions
JPS567332B2 (en]
Inventor
Yasoji Suzuki
Ryuzo Shiraki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP10913977A priority Critical patent/JPS5442949A/ja
Priority to US05/941,256 priority patent/US4217502A/en
Publication of JPS5442949A publication Critical patent/JPS5442949A/ja
Publication of JPS567332B2 publication Critical patent/JPS567332B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)
JP10913977A 1977-09-10 1977-09-10 Ternary converter circuit Granted JPS5442949A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP10913977A JPS5442949A (en) 1977-09-10 1977-09-10 Ternary converter circuit
US05/941,256 US4217502A (en) 1977-09-10 1978-09-11 Converter producing three output states

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10913977A JPS5442949A (en) 1977-09-10 1977-09-10 Ternary converter circuit

Publications (2)

Publication Number Publication Date
JPS5442949A true JPS5442949A (en) 1979-04-05
JPS567332B2 JPS567332B2 (en]) 1981-02-17

Family

ID=14502576

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10913977A Granted JPS5442949A (en) 1977-09-10 1977-09-10 Ternary converter circuit

Country Status (1)

Country Link
JP (1) JPS5442949A (en])

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57203334A (en) * 1981-06-08 1982-12-13 Mitsubishi Electric Corp Semiconductor integrated circuit device
JPS6016727A (ja) * 1984-06-08 1985-01-28 Hitachi Ltd Ｍｏｓトランジスタ回路
JPH0197014A (ja) * 1987-10-09 1989-04-14 Toshiba Corp 半導体集積回路
JPH04117029A (ja) * 1990-08-31 1992-04-17 Nec Ic Microcomput Syst Ltd レベルダウン回路

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60190033U (ja) * 1984-05-29 1985-12-16 株式会社東芝 高周波回路
JPH01130506U (en]) * 1988-02-29 1989-09-05

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57203334A (en) * 1981-06-08 1982-12-13 Mitsubishi Electric Corp Semiconductor integrated circuit device
JPS6016727A (ja) * 1984-06-08 1985-01-28 Hitachi Ltd Ｍｏｓトランジスタ回路
JPH0197014A (ja) * 1987-10-09 1989-04-14 Toshiba Corp 半導体集積回路
JPH04117029A (ja) * 1990-08-31 1992-04-17 Nec Ic Microcomput Syst Ltd レベルダウン回路

Also Published As

Publication number Publication date
JPS567332B2 (en]) 1981-02-17

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